Finite State Machines (FSM), as known, have long been an integral part of digital logic designs (which involve circuits operating on binary values, i.e. ‘0’ and ‘1’, or also called OFF and ON states, or logic ‘0’ and logic ‘1’ states) and are found in a majority of ASIC (Application-Specific Integrated Circuit) and FPGA (Field-Programmable Gate Array) designs. Modern digital electronic designs, however, have become susceptible to errors for a variety of reasons; generally, a digital system is said to be “in error” if one or more logic values in it are inadvertently flipped (e.g., a “0” becomes a “1” or vice versa). Such reasons include, but by no means are limited to, alpha particle radiations (e.g., space applications), Electronic-Magnetic Interference (EMI) (especially with electronic appliances in the vicinity), and harsh environmental conditions (e.g., as found in military applications). With increasing clock frequencies and shrinking transistor sizes, there are more leakage currents and greater cross talk in today's ASICs and FPGAs.
Most digital designs have a data path and a control path, and there is virtually an equivalent likelihood of an error occurring in either control path or data path and thereby causing the system to malfunction. When logic value changes (errors) occur in the data path, the data gets corrupted, and when such errors occur in the control path, the system may generally exhibit faulty behavior. Some errors are recoverable while others are not; recoverable errors include those from which the malfunctioning system can be eventually recovered with at worst a temporary loss of data and system run time. On the other hand, non-recoverable errors put the system in a dead-lock state or cause the system to hang (enter a dead-lock condition), and a manual reset of the system may be required.
In case of FSMs, when the value of one or more inputs to the flip-flops that hold the current state value are inadvertently flipped by error-causing conditions, the system may enter a dead-lock condition (hang) in some cases. When the system enters a dead-lock state the only way out would be a reset of the system.
There are many critical applications where resetting the system may not always be possible. For example, embedded systems used in automobiles in motion, or that assist in surgical processes, in space exploration missions, or in applications where live data is being processed, would all not lend themselves to a reset, and many more examples of course exist. In some applications though, a system reset is indeed possible, while this still leads to some degree of inconvenience. Examples of such applications include, but of course are not limited to, e.g., embedded applications used in home appliances such as refrigerators and DVD players, etc., and server applications processing huge amounts of data.
Currently, a widely used technique that addresses FSM state errors to some degree is “one-hot” encoding. A general discussion of one-hot encoding may be found in Alfke, Peter, “Accelerate FPGA Macros with One-hot Approach”, Electronic Design, Sep. 13, 1990. The disadvantages of this technique, however, are many and include the following:                The number of bits needed is linearly proportionate to the number of states, so more area is needed (i.e., more flip flops are needed than in other encoding methods) and the decoding of states takes considerable time.        The probability of error occurrence is greater (proportional to the bit length).        The technique will not work if two bits (including the active state bit) are flipped by an error.        The technique is limited to error detection only, and not at all to error prevention.        
Accordingly, compelling needs have been recognized in connection with improving upon the shortcomings and disadvantages of conventional methods and arrangements for addressing FSM state errors.